We present a simulation-to-silicon security characterization of microarchitectural side channels on open-source RISC-V cores. Twenty-three attack classes are measured across a six-core corpus that spans the design space from simple in-order pipelines (Rocket, VexiiRiscv) through a single-issue in-order core (CVA6) to a...
Jyotiprakash Mishra, Sanjay K. Sahay, Swati Mishra et al.· Chips· 0 citations
PACE is presented, a page-adaptive, cache-anchored memory encryption engine for RISC-V that makes nth-order DPA resistance practical and keeps cryptographic latency off the cache eviction critical path and demonstrates side-channel-hardened memory encryption on open RISC-V hardware.
Jyotiprakash Mishra, Sanjay K. Sahay, Swati Mishra et al.· Chips· 0 citations
The proposed FuseMD-XNet is a multimodal transformer-based framework that integrates dermoscopic images with structured patient metadata that employs intermediate fusion through feature concatenation and cosine similarity alignment, followed by adaptive certainty-guided fusion to dynamically weigh the modality contribu...
Akbar Kushanoor, Sanjay K. Sahay· Medical Image Analysis· 0 citations
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