Author

S. Prasad

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Open access Aug 2026

Hardware-level data layout approach to mitigate the memory row conflicts on FPGA-based CNN accelerators

A hardware-level data layout technique using a memory-centric accelerator architecture that improves memory performance in FPGA-based CNN accelerators in a scalable and hardware-efficient manner without requiring a large computational burden.

S. Prasad, Suman Jayakumar, Bellary Kursheed et al. · Bulletin of Electrical Engin... · 0 citations