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R. Rughinis

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#software testing Open access Sep 2026

Hardware-Assisted Spatial Memory Safety for Shared GPU Accelerators: A Pointer Tagging Co-Design with Analytical and Synthesis-Level Evaluation

Graphics processing units (GPUs) underpin high-performance computing, but device partitioning does not ensure that an in-context pointer remains within its allocation. We present a hardware–software co-design whose 16-bit tag uses odd parity and fail-safe class encoding. It combines a variable-precision extent, an aligned CRC checker, and an exact-bounds micro-cache. For 200,000 log-uniform requests from 16 B to 1 TiB, mean Class 4 fragmentation is 1.638%, versus 27.733% for power-of-two encoding. The seven-bit aligned signature has full GF(2) rank and a 1/128 non-adaptive collision rate; its deterministic window is exactly one through three regions and tight at four. Exhaustive testing rejects every one-bit tag corruption, while two-bit analysis demonstrates why parity is not adversarial authentication. A SAT-equivalent endpoint rewrite reduces Class 3 generic depth from 60 to 24 levels. A fail-closed 32-lane Class 4 topology detects nonuniform active-lane tags in hardware; for uniform tags, it reduces generic CMOS cost from 155,200 to 72,872 transistor equivalents (53.05%) and depth from 67 to 61 levels. Official SASS traces provide an analytical exposure bound rather than native simulation; a separate pre-layout 45 nm mapping is reported only as a timing sensitivity experiment.

Dan Toderici, T. Enache, R. Rughinis et al. · 0 citations
Open access Aug 2026

From Logging Configuration to Code Execution: A Systematization of Log4j 2 File-Write Primitives in HTTP-Exposed JMX

Java middleware may expose Java Management Extensions (JMX) through Jolokia’s Hypertext Transfer Protocol (HTTP) bridge. In affected ActiveMQ deployments, reachable Log4j 2 configuration managed beans (MBeans) become write capabilities and, with compatible triggers, enable remote code execution (RCE). We ask: in a specified product/version state, which writes and triggers compose into RCE, and which operational guard first fails or remains unresolved? We synthesize two published case studies into an evidence-coded method. Four write and four trigger classes recover four observed chains, isolate one model-implied pairing, and reject dependency-level candidates through failed or unresolved guards. It distinguishes ActiveMQ paths from documentation-limited Apache James, WildFly, Apache Karaf, and Red Hat AMQ cases. Egress filtering and static-file ownership do not stop every observed chain. Observed (O), derived (D), and model-implied (H) labels separate findings from hypotheses. The contribution is a falsifiable, product- and version-scoped management-plane instrument, not a new attack-stage sequence.

A. Caciulescu, Matei Badanoiu, R. Rughinis et al. · 0 citations
Open access Jul 2026

Object-Centric 2D-to-3D Pipeline for Interior-Design Visualization: Reference-Free Asset Evaluation and a Structured3D Scene-Level Benchmark

The results demonstrate the feasibility of integrating perception, 3D reconstruction, semantic assessment, and scalable deployment into a single applied pipeline, while remaining proof-of-concept and requiring extension to larger object and scene corpora, baselines, real-photograph evaluation, and human-centered assessment before broad claims about general interior-scene reconstruction can be made.

Dan Toderici, Tiberiu-Gabriel Rodanciuc, George-Alexandru Micu et al. · 0 citations

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