Radix-4 carry-save adder based accumulator for high-performance MAC units in factored systolic array accelerators
Abstract Machine learning workloads impose extreme computational demands on hardware, driving the adoption of domain-specific accelerators built around Systolic Arrays (SAs). Factored Systolic Arrays (FSAs) based on Radix-8 Booth multiplications reduce multiplier complexity by relocating the encoding logic to the array periphery, thereby simplifying each Processing Element (PE). Despite this multiplier-side enhancement, the Multiply-Accumulate (MAC) unit’s accumulation stage continues to impose a critical bottleneck when implemented with a standard Ripple Carry Adder (RCA), whose carry-propagation delay scales linearly with the accumulator width. This paper presents a Radix-4 Carry-Save Adder (CSA) accumulator within the Radix-8 FSA MAC and evaluates it on the Xilinx Spartan-3E FPGA design suite 14.7. The proposed architecture significantly achieves 22.5%, 21.3%, 24.5% and 4.3% reductions in critical-path delay, LUT, Slice utilization and Power consumption relative to the RCA baseline. Further, as approximate computing has emerged as a promising solution for enhanced efficiency, a lower-part OR Adder variant is evaluated, achieving the best power-delay product (2204 pJ). Optimization within FSA MACs enables high-throughput Machine Learning acceleration.