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P. Karule

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Open access Jul 2026

An Integrated Framework for High-Precision and Low-Power Computing

Purpose: The goal of this research is to create a unified computational framework that addresses the shortcomings of IEEE-754 floating-point arithmetic by enhancing the equilibrium among precision, dynamic range, and hardware resource efficiency. Design / Methodology / Approach: The proposed method integrates Posit number representation, Newton-Raphson-based division, SIMD-based parallel execution, and pipeline optimisation techniques into a single hybrid computational framework. Posit arithmetic is used to increase accuracy with fewer bits, and Newton-Raphson iterations are used instead of hardware dividers to reduce latency. The data were analysed via comparative performance evaluation through simulation experiments. Performance ratios, percentage improvements, and graphs were used to analyse the results and assess improvements in accuracy, speed, parallel processing, and energy efficiency. Research Limitation: The present implementation and assessment are confined to simulated or regulated computational settings and particular nonlinear workloads. The framework has not been validated across all floating-point workloads or various real-time hardware platforms, which may impact its generalisability. Findings: The input/design variables, processing variables, and performance/output variables cut the bit-width by 20–30% compared to IEEE-754 and make numbers more accurate by up to 35%. Precision up to 10−610^{-6}10−6 is reached within three Newton–Raphson iterations, which cuts division latency by 40–50%. SIMD execution increases throughput by 60–70% and energy efficiency by about 20%. Optimising the pipeline cuts latency by 30% to 40%. In general, the design reduces hardware space by up to 20% and improves energy efficiency by 18%. Practical Implication: The suggested framework can be used effectively in high-performance computing systems, embedded processors, and AI accelerators to achieve higher numerical accuracy, use less hardware space and power, and increase data throughput without complicating the architecture. Social Implication: The proposed arithmetic framework supports sustainable computing practices by enabling more accurate, energy-efficient computing. Originality / Value: This study introduces a unique combination of Posit arithmetic, iterative division, SIMD parallelisation, and pipelining optimisation into a single framework. The overall benefits to precision, latency, hardware area, and energy efficiency make it a unique and scalable solution for next-generation computing.

K. Pande, P. Karule · 0 citations
Open access Aug 2026

Deep Learning-Augmented Design of Floating-Point Arithmetic Units for High-Performance Nonlinear Computations

Nonlinear computations plays a critical role in modern applications such as deep learning, digital signal processing, cryptography, and scientific modelling, yet conventional IEEE-754 floating-point units struggle to meet the conflicting demands of high precision, low latency, and energy efficiency. Static data paths, fixed-precision formats, and polynomial-based approximations limit their adaptability and numerical robustness, particularly for transcendental and nonlinear operations. In this work, a deep learning–augmented floating-point arithmetic architecture is proposed to address these limitations. The architecture integrates five complementary learning-enabled modules: adaptive latency optimization using a reinforcement learning–based micro-scheduler, context-aware runtime error estimation and compensation, dynamic bit-width control through precision-aware deep bandwidth scaling, gradient-informed neural approximation of nonlinear functions, and domain-aware transfer learning for rapid arithmetic unit adaptation across applications. The proposed design is evaluated using FPGA-based hardware–software co-simulation on representative workloads from neural networks, signal processing, and cryptographic domains. Experimental results show substantial improvements, including latency reductions of up to 63%, numerical error reduction exceeding 70% with accuracy within ±0.5 ULP, power savings of up to 59%, and area reductions beyond 40%. Furthermore, application-level validation demonstrates negligible degradation in inference accuracy and significant reductions in retraining overhead across domains. These results confirm that learning-augmented arithmetic units provide an effective and scalable solution for next-generation nonlinear floating-point computation.

K. Pande, P. Karule · 0 citations

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