RL-Driven 3D Clustering of Jscan Architecture with Routing and Area Optimization in Chiplet Sip
Three-dimensional stacked ICs introduce new Design-for-Test (DfT) challenges due to high power density, routing congestion, and cross-tier connectivity constraints. In this work We propose 3D Joint-Scan, a tier-aware DfT architecture that extends the 2D Joint-scan framework to multi-tier 3D ICs and integrates reinforcement-learning-based (RL) physical-design optimization. Each tier combines clustered P-serial (MSS) and P-random (PRAS) scan structures with dual MISRs. We introduce RL driven scan flip-flops clustering in each layer to learn an optimal configuration to jointly minimize routing congestion and wire length while keeping the test power, test time, and data volume unchanged as base line. Experiments on scaled ISCAS89 benchmarks validate the proposed formulation to be efficient in dealing with routing congestion and area optimization. The design for test parameters such as test time, data volume, and test power are constrained within the given limits. The experimental results show the routing congestion reduction by 38% compared to the base line 2D and 3D JScan architecture. The complete 4-tier design is fully synthesized and place-and-routed in 65 nm technology with a maximum area reduction of 20% compared to baseline.