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Oct 2026
Understanding Real-World Ordering-Related Concurrency Bugs under Weak-Memory and Cross-Architecture Settings
Modern systems software is increasingly deployed across heterogeneous architectures such as x86, ARM, and RISC‑V, which provide substantially different memory-ordering guarantees. Under weak memory models, hardware and compilers may reorder memory operations or delay their visibility, causing concurrent code that appea...
Shao-Hao Wang, Cheng Wen, Yuan-Dao Cai et al.
· Proceedings of the 41st IEEE... · 0 citations