Author

Marwan Abdelwahab

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Jul 2026

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs

VeriRefine progressively refines the prose specification into an explicit, schema-constrained account of design intent, expressed as per-signal Abstract Signal Transition Functions (ASTFs) that commit each signal's logic style, clock domain, and reset behavior before any code exists and ground every behavior in a verbatim specification sentence.

Xiangfei Kong, Tasnim Tabassum, Marwan Abdelwahab et al. · arXiv.org · 0 citations