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Author

Lokesh Siddhu

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Open access Aug 2026

Retention-Aware RISC-V ISA Extension and Memory Controller on FPGA for MLC NVM

This paper presents a novel memory controller architecture and a RISC-V instruction set extension to optimize MLC NVM write operations by balancing speed and retention time, and introduces a fast-store instruction in RISC-V to increasing write performance while addressing retention limitations.

Mina Ibrahim, M. Shokry, Lokesh Siddhu et al. · 0 citations

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