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Author

Lingli Wang

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Preprint Aug 2026

StateTune: Transforming LLM-Assisted EDA Flow Tuning into a Stateful, Closed-Loop Process

EDA flow parameter tuning is critical for quality-of-results~(QoR), yet the parameter space is large, tightly coupled, and full evaluations are prohibitively expensive. Prior LLM-assisted tuners mainly use the LLM as an external proposer with transient working context; we instead present \textbf{StateTune}, which reformulates LLM-assisted EDA tuning as a closed-loop, state-carrying process. Its optimizer state is a typed, evidence-gated \emph{persistent optimization memory} that is updated by every evaluation and shared between candidate generation and budget allocation. On top of this optimizer state, an expected hypervolume improvement (EHVI)-guided, runtime-aware promotion policy ranks quick-stage candidates by expected Pareto frontier gain per unit of runtime cost. Evaluated on a Cadence industrial flow across six benchmark blocks (two technology nodes \(\times\) three designs), against five baselines including LLM+retrieval-augmented generation (RAG) and preference-based Bayesian optimization (BO) tuners, StateTune achieves the strongest final hypervolume on all six benchmark blocks, showing a stable improvement in frontier quality across the full matrix; it also matches or surpasses the strongest baselines on worst negative slack (WNS), area, and power across the same set. Ablation shows persistent memory is the largest contributor: removing it costs 58.5\% of the hypervolume. Dedicated analyses of evidence-gating sensitivity, memory poisoning, cross-design transfer, and three-seed reproducibility (CV\,\(<\)\,7\% on five of six blocks) further validate the memory design.

Kunlong Li, Shangshang Yao, Su Zheng et al. · 0 citations
Aug 2026

Cut Topology-Based FPGA Logic Architecture with Powerful Logic Capacity and Area Efficiency

Field-programmable gate arrays (FPGAs) have been an efficient alternative of implementation for digital circuits. Look-up table (LUT)-based programmable logic blocks (PLBs) serve as the foundation for FPGAs. As increasing the LUT input number to improve performance and logic capacity will introduce exponential area overhead, substantial research has focused on designing more efficient logic architecture. Previous approaches primarily design dedicated hardware by analyzing the frequency distribution of Boolean functions and implementing those with high frequency. However, these approaches face scalability challenges due to the explosive growth in the function space. In this paper, we consider the topology of cuts rather than Boolean functions they represent. By identifying topologies that occur commonly in cuts and integrating them with LUTs, we propose a new 8-input PLB architecture, named FLAIC. This architecture incurs only a slight area overhead compared to a 6-LUT while achieving logic capacity comparable to that of an 8-LUT. Post-synthesis results on VTR and Koios benchmarks demonstrate that FLAIC reduces the logic levels by over 20% compared to 6-LUTs. Additionally, post-implementation results show improvement in critical path delay by 11.9% and reduction in the number of Configurable Logic Blocks by 1.5% without sacrificing routability, compared to Intel Stratix 10-like architecture

Xianfeng Cao, Jiangnan Li, Chenyu Jiang et al. · 0 citations

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