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Author

Ling-Li Wang

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Preprint Aug 2026

PACT: Post-route Agentic Checkpoint Tuning for FPGA Timing Closure

PACT is presented, a Post-route Agentic Checkpoint Tuning framework for Vivado design checkpoints (DCP), which represents post-route tuning as validation-gated transitions between accepted and candidate checkpoints.

Huan Lin, Kunlong Li, Ling-Li Wang et al. · 0 citations
Preprint Aug 2026

StateTune: Transforming LLM-Assisted EDA Flow Tuning into a Stateful, Closed-Loop Process

StateTune is presented, which reformulates LLM-assisted EDA tuning as a closed-loop, state-carrying process that achieves the strongest final hypervolume on all six benchmark blocks, showing a stable improvement in frontier quality across the full matrix.

Kunlong Li, Shang-Shang Yao, Su Zheng et al. · 0 citations
Aug 2026

Cut Topology-Based FPGA Logic Architecture with Powerful Logic Capacity and Area Efficiency

This paper considers the topology of cuts rather than Boolean functions they represent and proposes a new 8-input PLB architecture, named FLAIC, which incurs only a slight area overhead compared to a 6-LUT while achieving logic capacity comparable to that of an 8-LUT.

Xianfeng Cao, Jiang-Nan Li, Chenyu Jiang et al. · 0 citations

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