Ke-Jian Feng

VeriBugBench: An Empirically Grounded Framework for Constructing Verilog RTL Debugging Benchmarks

RTL source-level debugging research requires benchmark artifacts that provide faulty designs together with precise change locations, executable test stimuli, and reproducible configurations. Available Verilog resources usually provide only a subset of these elements. We present VeriBugBench, a framework for constructin...