Page swapping remains the dominant mechanism for extending physical memory in modern operating systems. Despite the emergence of new memory technologies, swap-based memory extension continues to be widely deployed due to its transparency and compatibility with diverse storage backends. However, current Linux swap management relies on a simple priority-based policy when multiple heterogeneous backends are available, and is oblivious to page reuse behavior. As a result, fast devices are often occupied by pages that are rarely reused, while frequently refaulted pages are placed on slow devices, leading to unnecessary performance degradation under memory pressure. We present PagePilot, a reuse-aware page offloading framework for heterogeneous swap systems. PagePilot persistently tracks refault behavior across eviction and refault cycles and uses average refault distance to guide backend selection. In addition, a background migration mechanism corrects misplacements to preserve fast-device capacity for pages with imminent reuse. We implement PagePilot in the Linux 6.3 kernel and evaluate it using representative data-serving and analytics workloads. Our results show that PagePilot improves application throughput and reduces page-fault handling latency under memory pressure, while substantially increasing the fraction of refaults served by fast backends.
Xing-Ze Liu, Jiayan Dong, Xin-Yue Liu et al.· ACM Transactions on Architec...· 0 citations
: Memory-unsafe languages such as C and C ++ remain widely used because they provide low-level control and high performance, but they remain vulnerable to spatial and temporal memory-safety violations such as out-of-bounds accesses, buffer overflows, and use-after-free errors. Prior hardware-assisted defenses reduce software overhead, yet many still rely on CPU-side metadata checks that add latency to the critical path and often miss DMA-originated accesses. We show that metadata-access cost is not dominated solely by DRAM latency: a substantial portion of the delay comes from on-chip traversal and cache-related processing. Motivated by this result, we propose SerMC, a memory-controller-based tripwire mechanism that validates accesses when metadata arrives from Dynamic Random Access Memory (DRAM) and extends enforcement to DRAM-bound accesses issued by both processors and DMA-capable devices. SerMC keeps metadata checks off the CPU critical path while preserving compatibility with existing C/C ++ programs. The design targets spatial and temporal violations that cross tripwire-protected DRAM regions; non-linear pointer corruption that avoids such regions and microarchitectural side channels remain outside the scope of the current design. Our evaluation on selected SPEC CPU workloads shows 9.25% average performance overhead, while the most memory-intensive workloads incur slowdowns of up to 50%. These results indicate that SerMC provides practical average-case overhead but still exposes a clear worst-case tradeoff when metadata traffic competes with demand memory requests.
Gen Xu, Li Lv, Jiayan Dong· Computers, Materials & C...· 0 citations
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