#machine learning
Jul 2026
FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTs
This paper proposes FPGN, an end-to-end physically-aware framework that closes the gap between LUT-native learning and latency-optimized FPGA implementation, and addresses challenges through a hardware-aligned differentiable formulation for training FPGA-native LUT neurons.
Jia-Wei Liang, Haotong Qin, Lin-Feng Du et al.
· arXiv.org · 1 citation