Bridging Stochastic Interference and Deterministic Scheduling: An Automated Design Framework for Heterogeneous Embedded Systems
The automated design of heterogeneous embedded systems faces a fundamental challenge: bridging the gap between stochastic latency induced by resource contention and the deterministic requirements of real-time constraints. To address this, we propose a Hybrid Stochastic-Deterministic Modeling framework for contention-aware performance inference. This framework integrates queuing-theoretic analysis with deterministic schedulability verification, providing accurate end-to-end latency prediction under uncertain workloads. Building on this analytical foundation, we develop a Dual Evolutionary Path Resource Mapping (DEP-RM) algorithm. This method decouples the optimization process into structural exploration and mapping refinement, effectively resolving the conflict between global architectural diversity and local scheduling precision through an adaptive interaction mechanism. Experimental evaluations on a physical heterogeneous embedded platform demonstrate that the proposed framework achieves a prediction deviation of less than 5.6% compared to actual measurements, while the optimization algorithm reduces the global system execution time by approximately 40.7% against baseline designs. Note to Practitioners—This paper is motivated by the increasing difficulty of deploying complex real-time applications onto heterogeneous embedded platforms. In practical engineering, ensuring timing reliability is challenging because resource contention (such as shared memory conflicts) introduces unpredictable delays that traditional static tools often miss. This paper addresses this problem by introducing an automated resource mapping framework that explicitly models these stochastic hardware behaviors using a hybrid analytical approach. We present a dual-path optimization algorithm that automatically determines the best allocation of software tasks to hardware units. Experimental results on a physical multi-core platform demonstrate that this method can predict system latency with over 94% accuracy and reduce execution time by approximately 40% compared to manual or baseline designs. For practitioners, this implies a significant reduction in the “trial-and-error” design cycle for safety-critical systems, enabling more efficient utilization of heterogeneous hardware resources without compromising real-time guarantees.