Validity-Preserving Hierarchical RL for Joint Routing and Switch Placement in EDA
Routing and switch placement are fundamental combinatorial optimization problems in chip design, requiring the joint optimization of routing topology and physical placement under strict structural, geometric and logical constraints. Existing approaches typically rely on carefully engineered heuristics that incorporate...
Dorian Gailhard, Ugo Lecerf, Enzo Tartaglione et al.
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