Graphics processing units (GPUs) underpin high-performance computing, but device partitioning does not ensure that an in-context pointer remains within its allocation. We present a hardware–software co-design whose 16-bit tag uses odd parity and fail-safe class encoding. It combines a variable-precision extent, an aligned CRC checker, and an exact-bounds micro-cache. For 200,000 log-uniform requests from 16 B to 1 TiB, mean Class 4 fragmentation is 1.638%, versus 27.733% for power-of-two encoding. The seven-bit aligned signature has full GF(2) rank and a 1/128 non-adaptive collision rate; its deterministic window is exactly one through three regions and tight at four. Exhaustive testing rejects every one-bit tag corruption, while two-bit analysis demonstrates why parity is not adversarial authentication. A SAT-equivalent endpoint rewrite reduces Class 3 generic depth from 60 to 24 levels. A fail-closed 32-lane Class 4 topology detects nonuniform active-lane tags in hardware; for uniform tags, it reduces generic CMOS cost from 155,200 to 72,872 transistor equivalents (53.05%) and depth from 67 to 61 levels. Official SASS traces provide an analytical exposure bound rather than native simulation; a separate pre-layout 45 nm mapping is reported only as a timing sensitivity experiment.
Dan Toderici, T. Enache, R. Rughinis et al.· Computers· 0 citations
Electric motors are essential components of industrial systems and are extensively used in applications such as fans, pumps, compressors, and conveyors. As energy conversion devices, they typically operate with high rated efficiency, particularly in the case of medium- and high-power motors. However, the actual operating efficiency may be significantly reduced when motors are affected by faults or degradation mechanisms. Such faults introduce additional electrical, mechanical, and thermal losses, leading to increased energy consumption that is not converted into useful mechanical output.
This paper presents an experimental investigation of the influence of different fault types on the efficiency of induction motors. Several representative fault conditions are examined, including broken rotor bars, stator asymmetries, misalignments and loosened bolts, cooling system deficiencies, and insulation degradation. For each fault scenario, efficiency curves are obtained under a wide range of load levels and fault severities using a controlled laboratory test bench.
The experimental results demonstrate that all investigated faults lead to measurable efficiency reductions across the entire operating range, with increasingly pronounced effects as fault severity rises and as the motor operates near rated load conditions. These findings confirm that motor faults impact not only operational reliability but also energy efficiency, often resulting in hidden energy losses during prolonged operation. Consequently, the study highlights the importance of condition monitoring and maintenance strategies as effective tools for preventing failures and ensuring energy-efficient operation of industrial electric motors.
J. Antonino-Daviu, Jonathan Herrera-Guachamin, Larisa Dunai et al.· Electrotehnică, electronică,...· 0 citations
Java middleware may expose Java Management Extensions (JMX) through Jolokia’s Hypertext Transfer Protocol (HTTP) bridge. In affected ActiveMQ deployments, reachable Log4j 2 configuration managed beans (MBeans) become write capabilities and, with compatible triggers, enable remote code execution (RCE). We ask: in a specified product/version state, which writes and triggers compose into RCE, and which operational guard first fails or remains unresolved? We synthesize two published case studies into an evidence-coded method. Four write and four trigger classes recover four observed chains, isolate one model-implied pairing, and reject dependency-level candidates through failed or unresolved guards. It distinguishes ActiveMQ paths from documentation-limited Apache James, WildFly, Apache Karaf, and Red Hat AMQ cases. Egress filtering and static-file ownership do not stop every observed chain. Observed (O), derived (D), and model-implied (H) labels separate findings from hypotheses. The contribution is a falsifiable, product- and version-scoped management-plane instrument, not a new attack-stage sequence.
A. Caciulescu, Matei Badanoiu, R. Rughinis et al.· Computers· 0 citations
The results demonstrate the feasibility of integrating perception, 3D reconstruction, semantic assessment, and scalable deployment into a single applied pipeline, while remaining proof-of-concept and requiring extension to larger object and scene corpora, baselines, real-photograph evaluation, and human-centered assessment before broad claims about general interior-scene reconstruction can be made.
Dan Toderici, Tiberiu-Gabriel Rodanciuc, George-Alexandru Micu et al.· Electronics· 0 citations
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