D. K. Jarwal

Device-Circuit Co-Design Investigation of a Structurally Engineered 7-nm InGaAs-SOI Complementary FinFET for Wide-Temperature CMOS Operation

In this work, we report a structurally optimized design of 7-nm InGaAs-SOI complementary FinFET, and demonstrate thermal reliability of InGaAs-based logic device and circuit-level behavior over a wide temperature range of ˜200 to ˜700 K. The proposed 7-nm InGaAs–SOI FinFET with optimized fin architecture achieves Vth...