LATCH: LLM-Assisted Timing Closure Harness for Post-Route FPGA Optimisation
LATCH (LLM-Ass Timing Closure Harness), a two-layer framework that separates large language model (LLM) orchestration from deterministic FPGA implementation and evaluation, is presented.
Shuang-Long Gu, Matthew Youngman, Yu-Qin Zhao et al.
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