ITP-STDP: A Hardware-Efficient Intrinsic-Timing Power-of-Two Synaptic Learning Engine for On-Chip SNNs
Intrinsic-timing power-of-two STDP (ITP-STDP) and its corresponding prototype learning engine hardware architecture are presented and demonstrate superior energy efficiency, higher operating speed, and substantially lower hardware resource utilization.
Haihang Xia, Xin-Yu Zhao, Xuecheng Wang et al.
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