Christian Lanius

Design, Stability Improvement, and Scaling of a 4-Transistor Static Latch for Digital Compute-in-Memory

This work presents a novel standard cell-compliant static latch that can be placed alongside digital logic and investigates the use of backgate biasing to improve system stability, and draws a comparison between the 22 nm implementations from the original work and the 12 nm implementation, indicating that moving to fin...