Sub-Microsecond Deterministic Inference Processor via 3D Heterogeneous Integration of Thin-Film Lithium Niobate Acoustic Resonators on 28nm eRRAM/SOT-MRAM CMOS
Modern deep learning accelerators (GPUs, TPUs) are fundamentally constrained by the von Neumann memory wall: over 90% of total inference energy and latency is consumed by shuttling high-precision matrix weights across off-chip memory hierarchies (HBM3e, GDDR6) rather than executing arithmetic operations. Furthermore, a...