Author

Chenyu Jiang

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Aug 2026

Cut Topology-Based FPGA Logic Architecture with Powerful Logic Capacity and Area Efficiency

This paper considers the topology of cuts rather than Boolean functions they represent and proposes a new 8-input PLB architecture, named FLAIC, which incurs only a slight area overhead compared to a 6-LUT while achieving logic capacity comparable to that of an 8-LUT.

Xianfeng Cao, Jiang-Nan Li, Chenyu Jiang et al. · ACM Transactions on Reconfig... · 0 citations