Self-modifying code (SMC) is a specialized technique that alters program execution by modifying instructions in executable memory pages during runtime. While historically employed for performance tuning, dynamic optimization, and obfuscation, both x86 and RISC-V-based processors continue to support SMC as part of their architectural flexibility. However, the same capability that enables adaptive and high-performance execution also opens the door for novel microarchitectural exploitation. In particular, SMC allows attackers to induce distinctive instruction fetch and cache behaviors, thereby enabling precise monitoring of shared microarchitectural resources such as instruction caches. In this paper, we present the first in-depth security study of SMC on the latest Intel microarchitectures, including the latest hybrid CPU designs that balance performance and energy efficiency. We systematically analyze a set of x86 instructions that directly or indirectly invalidate instruction cache lines, revealing measurable timing asymmetries between cache hits and misses. Our results show that these SMC-induced timing artifacts can be leveraged to mount high-resolution cache attacks that are both stealthier and more reliable than traditional techniques. We demonstrate the power of our approach through two privacy-violating case studies: (1) recovering victim keystrokes with high accuracy in real time, and (2) performing website fingerprinting on hyper-threaded CPU cores, successfully targeting both the Google Chrome and Tor browsers. Beyond empirical results, we explore the architectural conditions that amplify SMC side effects, discuss the broader implications for multi-tenant and browser-based environments, and give an overview of possible hardware and software-level countermeasures.
Seonghun Son, Daniel Moghimi, Berk Gulmezoglu· ACM Transactions on Architec...· 0 citations
Pavement performance prediction aims to forecast the future condition of pavement as accurately as possible, enabling proactive planning and optimized maintenance and rehabilitation (M&R) interventions. Pavement failure has traditionally been predetermined during the design stage when performance indicators such as the international roughness index (IRI), cracking, and other distresses exceed predefined thresholds. While such projections may be useful during material-selection phases, pavements often experience varying deterioration patterns over their service life, making original forecasts less reliable. To overcome these challenges, we propose to use advanced predictive models based on machine-learning techniques while leveraging text embeddings extracted from pretrained models. This study specifically presents two IRI prediction models: a long short-term memory model for forecasting IRI during long-term deterioration, and an artificial neural network model for predicting post-maintenance IRI. Our study further experiments with the semantic encoding power of different large language models, including transformer models, to provide numerical representations of raw maintenance logs. We show the importance of precise parameter selection for text-embedding models along with readily available pavement-design input parameters passed to a customized artificial neural network (ANN) model for post-maintenance IRI prediction. The proposed framework supports integration of a wide variety of maintenance actions, including complex scenarios involving multiple maintenance applications. We trained the models using data extracted from the long-term pavement performance (LTPP) database and obtained
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scores of 93% and 86% for IRI long-term deterioration and post-maintenance test datasets, respectively. These results underscore successful application of intelligent models across the pavement’s entire service life.
K. S. Oguntoye, H. Ceylan, Berk Gulmezoglu et al.· Transportation Research Reco...· 0 citations
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