Self-Verifed FIR Filter ASIC with Vedic Arithmetic and Han-Carlson Accumulation at 90-nm
Reliability-critical digital signal processing (DSP) datapaths increasingly demand built-in error detection without sacrificing throughput or silicon area. Existing concurrent-error-detection schemes for FIR filters typically rely on full residue-number-system datapaths, dual modular redundancy, or parity-checksum codes, all of which incur appreciable area or latency overhead. This paper presents the complete RTL-to-sign-off ASIC implementation of a 3-tap direct-form FIR filter in 90-nm CMOS that integrates three contributions in a single core: (i) an Urdhva-Tiryakbhyam Vedic 4×4-bit multiplier that issues all 16 partial products in parallel; (ii) a two-stage Han-Carlson parallel-prefix accumulator (HCA8 and HCA9) chosen for its lower fan-out than Kogge-Stone; and (iii) an online Verification Test Unit (VTU) implementing the casting-out-nines digit-sum identity, which produces five independent runtime validity flags (v1–v5) without adding latency to the registered output path. Cadence Genus synthesis at 100MHz produced 906 instances with a worst negative slack (WNS) of +4,941ps and a total negative slack (TNS) of zero. Cadence Innovus place-and-route closed the design at 887 cells in a 9,713μm2 core (approximately 70% utilisation, nine routing layers) with zero DRC, antenna, and metal-fill violations. A directed fault-injection study comprising 1,024 single-bit-flip campaigns on the multiplier and adder outputs achieved a 99.6% error detection rate, validating the VTU as a low-overhead alternative to TMR-based schemes for soft-error-resilient DSP cores.