Andrew Bonilla

How Far Does Replication Pay Off? A Throughput-Area Study of Brute-Force SAT on an ECP5 FPGA

SAT solving is a core computational challenge across hardware verification, electronic design, and planning; an FPGA can evaluate SAT candidates at hardware clock rates without software overhead, enabling sub-microsecond solving on small instances. Yet, the throughput-area tradeoffs of parallel FPGA SAT datapaths remai...